Low dropout regulators (LDOs) are an important kind of circuits in power management chips that are widely used in the fields of consumer electronics, medical electronics, and aerospace, etc., because of their characteristics of low noise, low cost, and low power consumption.
The LDO controls a power transistor by amplifying an error signal obtained from an output feedback, thereby providing an output current to drive the load. Essentially, the LDO is a voltage-controlled current source which adjusts the load current according to the output voltage, as shown in FIG. 1. The traditional full on-chip LDO (e.g. Cap-less LDO) includes an error amplifier (EA), a power transistor, a resistive feedback network, and a load capacitance. The basic working principle is that the resistive feedback network samples the output voltage to be differentially amplified with the reference voltage, and the load current is provided by controlling the power transistor.
As the power transistor has characteristic of high gain under light-load, in traditional on-chip LDO, the Miller capacitance is connected between the gate terminal and drain terminal of the power transistor in a bridging manner to separate a dominant pole located at the EA output and the non-dominant pole located at the LDO output, so as to ensure the stability of the loop. If the light-load current is small and the non-dominant pole moves closer to the low frequency, a large area of the Miller capacitance is required to separate the dominant and non-dominant poles, and the gain bandwidth product GBW of the loop is reduced. Due to limitations of bandwidth of EA and slew rate (SR), a certain delay is needed for charging and discharging the gate terminal capacitance of the power transistor by a current, the output capacitance is subjected to the load current during the delay, as a result, problems such as the undershoot of the output voltage is high and the time for establishing an overshoot is long etc. are caused.